Trying to meet the ever-increasing computing workload demands, monolithic silicon system-on-chip (SOC) has been integrating more and more features with the most advanced silicon technology nodes. However, the explosion in computation workload diversity makes no single system fits for all. Chiplet implementation uses a selection of modular dies, referred to as chiplets, to deliver an optimum feature solution. But optimizing the chiplet interconnect is a major challenge.
A new holistic methodology focusing on chiplets interconnect jitter modeling, which uses an analytical expression of power induced jitter and accumulation, is proposed and developed. The behavior model is correlated to an actual empirical measurement under different conditions of a High Bandwidth Memory (HBM) system platform. The model is then applied to form a set of output jitter Response Surface Model (RSM) which provides a contour to identify critical input parameters. The impact of input factors dependency, such as power noise tone frequencies, amplitudes, channel ground configurations, is examined. Empirical chiplet system measurement data will be used for correlations.