The consumer and market demand for higher data throughput has been pushing industries and standards to increase data rates. The evolution of other standards has also been pushing technologies such as PCIe to higher data rates. PCIe 5.0 with data rate of 32 GTPS had already introduced many Signal Integrity and design challenges. The conventional doubling of data rate for the next generation PCIe specification, PCIe6.0, has moved PCIe from the traditionally NRZ signaling to PAM4. While the handling of channel loss will be more manageable in PAM4, there are many new challenges in various stages of design and verification of a PCIe 6.0 System. In this panel discussion, we will focus on several aspects of the PCIe 6.0 Design and verification. We will discuss Signal Integrity Challenges, Crosstalk, Test and Measurement Challenges, with a deep dive about how to accurately measure SNDR with up to -dB of package loss plus break-out channel losses. We will also discuss the impact of SSC on SNDR measurement, how to accurately characterizing PCIe 6.0 transmitters, Simulation Challenges, Connector and cable requirements, use of retimers, as well as add-in card's requirements.