Power Integrity Principals for nm-CMOS Devices

Event Time

Originally Aired - Tuesday, August 17 11:10 AM - 11:50 AM

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Event Location

Location: Meeting Room 211AB

Event Information

Title: Power Integrity Principals for nm-CMOS Devices

Event Type: DesignCon - Technical Session

Pass Type: All-Access Pass, 2-Day Pass


Common concept of Power Integrity  "Target impedance", created over two decades ago and proposed "low and flat" PDN impedance. Widely adopted in the Industry by IC designers and EDA companies this concept still dominate as the de-facto industry standard.  When CMOS devices reached 120-nm it has been noted that using this approach leads to rising voltage variations in PDN. Research in Power Integrity have brought many useful improvements for the last 10 years, but not resulted in new concept that allow to design system of Chip-Package-PCB with low voltage variations in PDN. In majority of cases developers are still using an old concept at system and board design that might led to device and project failure. This work brings new PDN concept and Decoupling strategy that free from noted deficiencies.