The invention of high bandwidth memory (HBM) has led the development of high performance computing and artificial intelligence algorithms. However, critical problems to limit the next-generation HBM are not only signal, power, and thermal integrity, but also testability and reliability. In this paper, we proposed a wireless memory test scheme as a breakthrough solution for highly reliable next-generation HBM. The proposed scheme can wirelessly transfer the input test signal using a 300 GHz band on-chip patch antenna. A QPSK receiver integrated on the HBM logic die achieves a data rate of 2 Gbps with BER 10-9. The proposed wireless test scheme can achieve testability and increase the reliability by elimination of ATE to DUT channel loss in the conventional test system. Furthermore, existing direct access (DA) pads for test can be converted to signal and power pads with the wireless transmission of test signal. The additional signal and power pads can basically enhance the signal and power integrity of HBM. Especially in the conventional HBM pad map, the placement of test pads limits the directivity of IO interface. However, the proposed wireless test scheme enables a new interface architecture and reinvention of the existing HBM.