Plated-through-hole Via Design Specifications for 112-G Serial Links

Event Time

Originally Aired - Tuesday, August 17 12:10 PM - 12:50 PM

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Event Location

Location: Meeting Room 211AB


Event Information

Title: Plated-through-hole Via Design Specifications for 112-G Serial Links

Event Type: DesignCon - Technical Session

Pass Type: All-Access Pass, 2-Day Pass

Theme: Internet of Things (IoT)


Description

An earlier study of a high layer-count test board using plated-through-hole (PTH) and a limited quantity of laser vias was shown to be capable of supporting 112G PAM-4 links (or equivalent signaling having 28 GHz (Nyquist) bandwidth).  This board design was rebuilt by a different fabricator, and the test results revealed a significant decrease in the bandwidth of the vias.  These results led to development of a set of design specifications that PCB vendors can easily validate, which will ensure that the use of high layer-count boards with PTH technology are viable for emerging 112G PAM-4 links.


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