In order to better meet their performance and miniaturization goals manufacturers are looking for higher functionality for their semiconductor packages. For that reason, many manufacturers will rely heavily on more innovative IC package solutions, often integrating a number of already proven functional elements within a single-package outline. This capability has been stimulated by the rapid deployment of new semiconductor packaging innovations from a broad number of domestic and offshore competing companies that understand that new product time-to-market can be the difference between leading and following.
This course addresses the design and assembly challenges for developing and implementing a broad range of high-density semiconductor package methodologies and multiple function System-in-Package (SiP) technologies. Although integrating several semiconductor functions onto a single die element (System-on-Chip) appears to provide a viable solution for some, development cost and time has often proved to be excessive. On the other hand, many companies have realized that wafer and panel level packaging and integrating mature multiple-die elements within a 2D or 3D configured package actually proves to be superior to the multiple function SoC concepts because it maximizes source flexibility, minimizes risk, significantly reduces development time and cost.