A Case Study in the Development of a 112Gbps-PAM4 Silicon & Connector Test Platform

Event Time

Originally Aired - Tuesday, August 17 11:10 AM - 11:50 AM

Info Alert

Create or Log in to My Show Planner to see Videos and Resources.

Videos

Resources


{{video.title}}

Log in to your planner to join the zoom meeting!

{{chatHeaderContent}}

{{chatBodyContent}}

Resources

Info Alert

This Session Has Not Started Yet

Be sure to come back after the session starts to have access to session resources.

Event Location

Location: Exec Ballroom 210C


Event Information

Title: A Case Study in the Development of a 112Gbps-PAM4 Silicon & Connector Test Platform

Event Type: DesignCon - Technical Session

Pass Type: All-Access Pass, 2-Day Pass

Theme: High-speed Communications,Data Centers


Description

The continued progression to higher data rates puts increasing demands on the design of practical serdes channels. At 112G-PAM4, the UI is only 17.86ps, and signal transmission in the PCB must be highly optimized for loss, reflections, crosstalk and power integrity. This paper will describe the signal-integrity and power-integrity design process, show simulated SI and PI performance correlated to measured data as well as measured eye diagrams of a test board that uses a 112G-capable silicon and high-speed compression-mount cable connectors. The resulting test channel aims to meet the toughest reference test fixture insertion loss requirements of IEEE P802.3ck-100Gb/s and OIF CEI-112G PAM4 specifications.


Speakers


Tracks