Capacitor Placement Strategies for Optimum Power Integrity

Event Time

Originally Aired - Tuesday, August 17 9:00 AM - 9:40 AM

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Event Location

Location: Meeting Room 211CD

Event Information

Title: Capacitor Placement Strategies for Optimum Power Integrity

Event Type: DesignCon - Technical Session

Pass Type: All-Access Pass, 2-Day Pass


Power integrity engineers understand how parasitic path inductance combined with fast di/dt transients can lead to excessive voltage ripple.  Extensive studies have been made to show how this path inductance can be reduced for capacitor placement and mounting, but what about resonances between capacitors? Does it matter if a small ceramic capacitor is placed next to or below a large bulk capacitor?  How important is symmetry and at what frequency does it matter? These are just a few questions that still plague PI designers when leveraging data sheet designs.  

Trial and error or large matrixes of experiments can be cost and time prohibitive.  However, utilizing EM simulation to visualize current densities along with time and frequency domain analysis of the PDN can provide a lower cost and more robust design methodology.  Learn how resonant free power delivery does not just apply to the load, each capacitor location and the VRM must also be balanced to avoid PDN resonances that could ultimately lead to EMI problems.