Designing 224-G High Performance FPGA Package & Board with Confidence

Event Time

Originally Aired - Tuesday, August 17 12:10 PM - 12:50 PM

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Event Location

Location: Meeting Room 212AB

Event Information

Title: Designing 224-G High Performance FPGA Package & Board with Confidence

Event Type: DesignCon - Technical Session

Pass Type: All-Access Pass, 2-Day Pass

Theme: Consumer Electronics


In this paper, the signal integrity challenges in the 224G PAM4 BGA package and board design are uncovered and key enablement solutions are proposed. These challenges include higher-order mode propagation and dispersion, plane resonance, transmission loss, cross talk, vertical transition, and BGA ball pattern that is friendly for PCB breakout. When the system operation frequencies reach to or exceeds the cut-off frequency of a BGA package, higher-order modes can propagate in the package, causing energy spread, dispersion and ISI. In this work, the cut-off frequency versus the BGA ball pitch is investigated, the results can be used to guide the selection of BGA ball pitch for different applications. A localized skip-layer technology is introduced, and several design configurations are proposed that can reduce the propagation loss by half with the same dielectric material and copper surface roughness. This approach, however, will not impact the memory IO or power routing in the high-performance high-density FPGA package and board design. Some investigations of low dielectric-constant materials are also conducted for relaxing the SERDES equalization tap length required to compensate the package multi-reflection. The above stated approaches drive the key enablement solutions to a successful 224G high-performance FPGA package and board design.