100G Chip-to-Module Interface Challenges & New Measurement Methodology

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Originally Aired - Wednesday, August 18 3:00 PM - 3:40 PM

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Event Location

Location: Meeting Room 212AB


Event Information

Title: 100G Chip-to-Module Interface Challenges & New Measurement Methodology

Event Type: DesignCon - Technical Session

Pass Type: All-Access Pass, 2-Day Pass

Theme: High-speed Communications,Data Centers


Description

With increased insertion loss budget and signal integrity challenges, new reference receivers and measurement methodologies are being defined in the standard bodies for the 100G per-lane Chip-to-Module interface. This paper discusses the challenges that the industry faces: including channel design, SERDES performance and power trade off, and the new C2M interoperability compliance test methodologies. In particular, this paper provides in-depth analysis of reflection and TX optimization problems which are essential for low-power SERDES. Finally this paper will present real system measurement results with the being-developed IEEE 802.3ck  specification and measurement methodology.


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