FPGA, ASIC, and MCM component power rails often draw high currents to support intense processing and therefore require aggressive target impedances of 10mOhms and below. Supplier data sheets provide recommended decoupling capacitors and specify target impedances and frequency range for each power rail, without consideration of the component load. Consequently, board designers must rely on datasheet recommendations and live with uncertainty, or add as many additional decoupling capacitors the PCB (Printed Circuit Board) layout allows.
The purpose of this presentation is to offer a power integrity analysis methodology that considers the entire PDN (Power Distribution Network) ecology. The analysis considers the effects of the component die and package capacitors, PCB chip attach elements, PCB level decoupling, and Voltage Regulation Module (VRM) and its associated bulk decoupling. The methodology uses any spice tool available in the industry to integrate the component load, supplier recommended PCB capacitors, and VRM bulk decoupling capacitors. The result is PDN design that is a reasonable balance between robust design at the PCB level, and lower cost at the component level. The reward is a PDN design that is not over or under-designed, but well designed.